The performance of an integrated circuit device is improved mainly by minimizing its size and improving its operation speed. Currently, the characteristic size of the integrated circuit device (such as a MOSFET) has been minimized to be in a nano-scale. Under such a nano-scale, however, some limitations in principle and practice are raised, which impact the application of the integrated circuit technology based on the silicon planar CMOS technology. Generally, it is acknowledged that the CMOS technology has a chance to be used for the 20 nm-scale even 10 nm-scale. However, when used for a scale less than 20 nm, the conventional planar CMOS technology encounters many problems. In recent years, the multi-gate MOS technology among various new technologies has widely been researched and deemed as the most desirable technology for the use in the scale less than 20 nm, since the multi-gate device may be stronger for inhibiting the short channel, have better subthreshold characteristic and higher driving ability, and may result in a denser circuit, in comparison with the conventional single-gate device.
Currently, a FinFET device is the most desirable multi-gate device, since its self-aligned structure can be made by the conventional planar CMOS process. The FinFET device may include a dual-gate FinFET and a tri-gate FinFET. On the one hand, the thickness of a Fin of the dual-gate FinFET is required to be ⅓-½ of the length of the gate electrode in order to obtain an acceptable performance, which results in a big challenge to the fine processing. On the other hand, three faces of a Fin of the tri-gate FinFET are all controlled by the gate electrode. Thus, the tri-gate FinFET should have a strong ability of inhibiting the short channel. Accordingly, its Fin may have a thickness equal to or longer than the length of the gate electrode. That is, the (smallest) characteristic size of such a device is still the length of the gate electrode, which will not result in a problem to the fine processing. Thus, this technology would be more compatible with the conventional CMOS process. However, in practice and principle, a tri-gate FinFET with a heavy-droped channel has exhibited a desired performance in short channel, but a tri-gate FinFET with a light-droped or un-droped channel is not significantly better than the dual-gate FinFET. In the nano-scale, the MOS device should not take a heavy-droped channel in order to avoid discrete threshold voltage caused by the discrete impurity volume. That is, the channel of the MOS device should be light-droped or un-droped. In addition, with the same area of the channel, a tri-gate device occupies more area than a dual-gate device even than a single-gate device. As a result, the dual-gate FinFET device may be more desirable.
From the above, although the dual-gate FinFET device may be more desirable than the tri-gate FinFET device, some technical problems should be solved before the application thereof. A main problem to be solved is the processing for the ultra-thin Fin body. None of the reported fabricating technologies can be used for mass production. Generally, the Fin body is made by photolithography together with another subsequent technique, such as ashing to the etched pattern, in order to minimize the size of the pattern. However, such a technique cannot be used to manufacture circuits due to its bad uniformity and repeatability. Another possible choice is the spacer image transfer technique, which is a simple nano-scale processing technique and can be used to manufacture a single device. However, this technique may result in many parasitic patterns and therefore is not adaptable to manufacture circuits.